BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS

ABSTRACT

A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

RELATED APPLICATIONS

This application claims benefit of U.S. Provisional Application Ser. No.60/816,050, filed Jun. 23, 2006, the entire contents of which areincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor structures and methods offabricating the same. More particularly, the present invention relatesto a III-V compound semiconductor-containing heterostructure which canbe used as a buried channel of a field effect transistor (FET). Thepresent invention also provides a method of fabricating such a III-Vcompound semiconductor-containing heterostructure. In addition, thepresent invention also provides a method of forming a FET which includesthe inventive heterostructure as a buried channel.

BACKGROUND OF THE INVENTION

Compound semiconductors are receiving renewed attention for use aschannel materials for advanced ultra large scale integration (ULSI)digital logic applications due to their high electron hole mobility. Forexample, the InGaAs/InAlAs material system is one of the most promisingmaterial systems for this application due to its large conduction-bandoffsets and high carrier mobility. Schottky-gated InGaAs high electronmobility transistors (HEMTs) grown on InP substrates have producedmaximum transconductance g_(m) values over 2 S/mm (see, D. Xu et al.,IEEE Elec. Dev. Let., 20, 206 (1999)), and have been shown to comparefavorably in terms of a power-delay product (see, D. H. Kim et al., IEDMTech. Dig., 787, (2005)).

Despite these promising results, for ULSI applications, lnGaAs-channelfield effect transistors (FETs) will ultimately need to incorporate highdielectric constant (k) dielectrics as the gate dielectric in order tomeet current leakage requirements.

Previous work on InGaAs-channel metal oxide semiconductor field effecttransistors (MOSFETs) has mainly focused on surface-channel devicegeometries. See, for example, F. Ren, IEEE. Elec. Dev. Let., 19, 309(1998). Such devices, however, require the formation of an extremelyhigh quality semiconductor/dielectric interface in order to preserve alow interface state density near the surface-layer conduction band edge.

Despite the above advances in the art, integration of InGaAs-channelsfor FET applications still requires breakthrough in the following areas(i) surface passivation in conjunction with compatibility with high kgate dielectrics, (ii) quantum well engineering for scalability beyond22 nm CMOS technology, and (iii) low resistance in the source/drainregions. To date, the applicants are unaware of any prior art III-Vcompound semiconductor-containing structure that satisfies the threerequirements mentioned above.

In view of the above, there exists a need for providing a III-V compoundsemiconductor-containing heterostructure which can be used as a buriedchannel for FETs, including MOSFETs.

There also exists a need for providing a III-V compoundsemiconductor-containing heterostructure which provides (i) surfacepassivation in conjunction with compatibility with high k gatedielectrics, (ii) quantum well engineering for scalability beyond 22 nmCMOS technology, and (iii) low resistance in the source/drain regions.

SUMMARY OF THE INVENTION

The present invention provides a III-V compound semiconductor-containingheterostructure (i.e., a quantum well structure) which can be used as aburied channel for FETs. The inventive III-V compoundsemiconductor-containing heterostructure addresses the surfacepassivation problem mentioned above. In addition, the inventive IIII-Vcompound semiconductor-containing heterostructure can be scaled beyondthe 22 nm CMOS technology. Moreover, the inventive III-V compoundsemiconductor-containing heterostructure, when present in MOSFETincluding a selective epitaxial layer in the source/drain regions, canaide in reducing the resistance in the source/drain regions of the FET.

In the present invention, the term “III-V compound semiconductor”denotes a semiconductor material that includes at least one element fromGroup III of the Periodic Table of Elements and at least one elementfrom Group V of the Periodic Table of Elements. Typically, the III-Vcompound semiconductors are binary, ternary or quaternary alloysincluding III/V elements. Examples of III-V compound semiconductors thatcan be used in the present invention include, but are not limited toalloys of InGaAs, InAIAs, InAlAsSb, InAlAsP and InGaAsP.

The inventive III-V compound semiconductor-containing heterostructurecomprises, from bottom to top, a III-V compound semiconductor bufferlayer, a III-V compound semiconductor channel layer and a III-V compoundsemiconductor barrier layer. In the present invention, the barrier layerand the buffer layer are comprised of a III-V semiconductor materialthat each has a wider band gap than that of the III-V compoundsemiconductor channel layer. That is, the barrier layer and the bufferlayer are each composed of a III-V compound semiconductor having a bandgap that is larger than the band gap of the III-V compound semiconductorin the channel layer. The term “band gap” refers to the energydifference between the top of the valence band (i.e., E_(V)) and thebottom of the conduction band (i.e., E_(C)). Typically, the buffer layeralso has a wide band gap as compared to the channel layer.

Since a wide band gap material is used for the barrier and buffer layersand a narrow band gap material is used for the channel layer, carriersare confined to the channel layer under certain gate bias range.Typically, the carriers are confined in the channel layer when typicalgate bias conditions are applied.

The inventive III-V compound semi conductor-containing heterostructureused for a buried channel MOSFET minimizes the stringent requirementsfor dielectric/III-V interfacial properties. In contrast and in priorart MOSFET structures including a surface channel III-V structure, ahigh density of traps at the dielectric/III-V interface exists whichprevents the formation of an inversion layer.

In addition, the inventive III-V compound semiconductor-containingheterostructure used for a buried channel MOSFET has a higher carriermobility compared to conventional surface channel III-V containingMOSFET structure due to a reduction in carrier scattering.

In general terms, the inventive III-V compound semiconductor-containingheterostructure comprises:

-   a III-V compound semiconductor buffer layer having a first band gap;-   a III-V compound semiconductor channel layer having a second band    gap located on an upper surface of said buffer layer; and-   a III-V compound semiconductor barrier layer having a third band gap    located on an upper surface of the III-V compound semiconductor    channel layer, wherein said first and third band gaps are larger    than the second band gap.

In some embodiments of the present invention, the barrier layer includesa doped region which is located in a lower region of the barrier layerthat abuts the interface with the underlying III-V compoundsemiconductor channel layer; such a doped region is referred to in theart as a delta doped region. When a doped region is present in thebarrier layer, the dopant atom may be an n-type dopant (i.e., an elementfrom Group IV or VI of the Periodic Table of Elements) or a p-typedopant (i.e., an element from Group II or VI of the Periodic Table ofElements). The concentration of dopant within the doped region istypically from about 10¹¹ to about 10¹⁵ atoms/cm², with a concentrationof dopant within the doped region from about 10¹¹ to about 10¹³atoms/cm² being more typical.

In yet another embodiment of the present invention, a III-V compoundsemiconductor cap layer can be located atop the III-V compoundsemiconductor barrier layer. When the III-V semiconductor cap layer ispresent, the cap layer is typically, but not always necessarily, a dopedlayer. The dopant within the III-V compound semiconductor cap layer canbe an n-type dopant or a p-type dopant, with an n-type dopant being moretypical for an n-MOSFET. Unlike the delta doped region described above,the doping within the cap layer is evenly distributed throughout theentire vertical thickness of the layer. The concentration of dopant withthe cap layer is typically from about 10¹⁷ to about 10²¹ atoms/cm³, witha concentration of dopant within the cap layer from about 10¹⁸ to about10²⁰ atoms/cm³ being more typical.

The cap layer may comprise the same or different III-V compoundsemiconductor as the channel layer. In a preferred embodiment of thepresent invention, the cap layer and the channel layer comprise the samematerial elements, but are of a different alloy composition.

In still another embodiment of the present invention, the barrier layerand the buffer layer are comprised of an alloy of InAlAs, while thechannel layer is comprised of an alloy of InGaAs. By “alloy of InAlAs”it is meant a composition of In_(x)Al_(1-x)As wherein x is from about 0to about 1, and more preferably from about 0.4 to about 0.6. In onehighly preferred embodiment of the present x is 0.52. By “alloy ofInGaAs” it is meant a composition of In_(y)Ga_(1-y)As wherein y is fromabout 0 to about 1, and more preferably y is from about 0.3 to about0.8. In a highly preferred embodiment of the present invention, y is0.7.

In a further embodiment of the present invention, each of the III-Vcompound semiconductor layers is a single crystal material of typicalcommercial quality. By “typical commercial quality” it is meant thateach of the III-V compound semiconductor layers have a defect density onthe order of about 10⁵ atoms/cm² or less, with a defect density of lessthan about 5000 atoms/cm² being more typical. The typical commercialquality of the III-V compound semiconductor layers is a result ofutilizing an epitaxial growth process such as, for example, molecularbeam epitaxy (MBE) or metalorgano chemical vapor deposition (MOCVD).

In addition to the above III-V compound semiconductor-containingheterostructure, the present invention also is directed to structures,such as, for example FETs, that contain the inventive III-V compoundsemiconductor-containing heterostructure as a buried channel. In thisaspect of the present invention, the semiconductor structure includes:

-   a semiconductor substrate having an upper surface;-   a buried channel structure located on said upper surface of said    semiconductor substrate, wherein said buried channel structure    comprises a III-V compound semiconductor buffer layer having a first    band gap, a III-V compound semiconductor channel layer having a    second band gap located on an upper surface of said buffer layer,    and a III-V compound semiconductor barrier layer having a third band    gap located on an upper surface of the III-V compound semiconductor    channel, wherein said first and third band gaps are larger than the    second band gap;-   a dielectric material having a dielectric constant of greater than    4.0 located on said buried channel structure and in contact with at    least a portion of said barrier layer;-   a gate conductor located on a portion of said dielectric material;    and-   a source contact and a drain contact which are in contact with at    least said channel layer.

Most of the embodiments mentioned above for the heterostructure applyhere as well for the FET-containing structure as well.

It is noted that in the inventive FET structure, the cap layer mentionedabove is a patterned III-V compound semiconductor cap layer that, ifpresent, is located atop the III-V compound semiconductor barrier layer.In embodiments in which the patterned cap layer is present, thepatterned cap layer has an opening that extends to a surface of theunderlying barrier layer. The dielectric material is present in theexposed barrier layer. In some embodiments, the dielectric material ispresent on the surface of the patterned cap layer as well as within theopening covering the exposed sidewalls of the patterned cap layer andthe exposed bottom portion of the barrier layer. In the embodimentincluding the patterned cap, the width of the opening defines the gatelength. In one embodiment, the channel length is less than or equal to260 nm. In some embodiments, the structure has a positive thresholdvoltage.

The dielectric material having a dielectric constant of greater than 4.0is referred to herein as a high k dielectric. Typically, the high kdielectric has a dielectric constant of about 7.0 or greater, with adielectric constant of about 10.0 or greater being even more typical.The dielectric constants mentioned herein are relative to a vacuum,unless otherwise stated. Specifically, the high k dielectric employed inthe present invention includes, but is not limited to an oxide, nitride,oxynitride and/or silicates including metal silicates, aluminates,titanates and nitrides. In one embodiment, it is preferred that the highk dielectric is comprised of HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃,LaAlO₃, Y₂O₃, a pervoskite oxide, HfSiO_(z), HfAlO_(z) orHfAlO_(a)N_(b). Preferably, the high k dielectric is a Hf-baseddielectric material.

The gate conductor of the present invention includes any conductivematerial such as, for example, polysilicon, polysilicon germanium,conductive metals, conductive metal alloys, conductive silicides,conductive nitrides and combinations or multilayers thereof. Preferably,the gate conductor is a conductive metal, with Al, Pt, Au, W and Tibeing highly preferred. The selection of metal gates is advantageoussince conductive metals have different workfunctions that permit one toadjust the threshold voltage of the device.

The source and drain contacts, which are on either side of the gateconductor, are typically comprised of a conductive material includingone of the conductive materials mentioned above for the gate conductor.

In some embodiments of the present invention, the barrier may include athin passivation layer. When present, the thin passivation layer maycomprise a thin layer of a chemical oxide. Alternatively, thepassivation layer may include a thin layer of amorphous Si/SiO₂ orGe/Si/SiO₂.

In addition to the above structures, the present invention also relatesto a method of fabricating such structures. With respect to theinventive III-V compound semiconductor-containing heterostructure, themethod includes:

-   first epitaxially growing a III-V compound semiconductor buffer    layer having a first band gap on an upper surface of a substrate;-   second epitaxially growing a III-V compound semiconductor channel    layer having a second band gap on an upper surface of the buffer    layer; and-   third epitaxially growing a III-V compound semiconductor barrier    layer having a third band gap on an upper surface of the III-V    compound semiconductor channel layer, wherein said first and third    band gaps are larger than the second band gap.

The substrate may also be a semiconductor substrate or a material stackcomprising at least a semiconductor substrate, In other embodiments, afourth step of epitaxially growing is performed that forms a III-Vcompound semiconductor cap layer on the surface of the barrier layer.

With respect to the inventive FET, the method includes the steps of:

-   forming a buried channel structure atop a semiconductor substrate,    wherein said forming includes first epitaxially growing a III-V    compound semiconductor buffer layer having a first band gap on an    upper surface of said semiconductor substrate, second epitaxially    growing a III-V compound semiconductor channel layer having a second    band gap on an upper surface of the buffer layer, and third    epitaxially growing a III-V compound semiconductor barrier layer    having a third band gap on an upper surface of the III-V compound    semiconductor channel layer, wherein said first and third band gaps    are larger than the second band gap;-   forming a dielectric material having a dielectric constant of    greater than 4.0 on said buried channel structure and in contact    with at least a portion of said barrier layer;-   forming a gate conductor on a portion of said dielectric material;    and-   forming a source contact and a drain contact which are in contact    with at least said channel layer.

Many of the above-mentioned embodiments are also applicable in formingthe inventive FET structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial representations (through a cross sectional view)illustrating a heterostructure of the present invention which issuitable for use in a buried channel MOSFET.

FIG. 2 is a pictorial representation (through a cross sectional view)illustrating another heterostructure of the present invention which issuitable for used in a buried-channel MOSFET; this heterostructurerepresents a highly preferred embodiment.

FIG. 3 is a pictorial representation (through a cross sectional view)illustrating a buried channel MOSFET using the heterostructure shown inFIG. 2

FIG. 4 is an energy band gap diagram and interface state densitydistribution corresponding to the structure of FIG. 3 in the gateregion.

FIG. 5 is a plot of drain current (mAmps/mm) vs. drain-to-source voltage(V) of a long channel MOSFET with L_(g)5 microns.

FIGS. 6A-6B are plots of the drain current (mAmps/mm) vs. gate-to-source(V) and extrinsic transconductance g_(m) (mS/mm) vs. gate-to-source (V),respectively, of a long channel MOSFET with L_(g)=5 microns.

FIG. 7 is a plot of gate current (A/cm²) vs. gate voltage (V) of a longchannel MOSFET (L_(g)=5 microns) with a prior art HEMT device.

FIG. 8 is a plot of capacitance (μF/cm²) vs. gate voltage (V) of aninventive buried channel MOSFET.

FIG. 9 is a plot of mobility (cm²/Vs) vs. carrier sheet density (10¹²cm⁻²) of an inventive buried channel MOSFET using 100 khz C-V data.

FIG. 10 is a plot of drain current (mAmps/mm) vs. drain-to-sourcevoltage (V) of a short channel MOSFET with L_(g)=260 nm.

FIG. 11 is a plot of drain current (mAmps/mm) vs. drain-to-sourcevoltage (V) of a short channel MOSFET with L_(g)=260 nm of a enhancementmode (EM) and a depletion mode (DM) short channel MOSFET with L_(g)=260nm.

FIG. 12. is a plot of transconductance (mS/mm) vs. gate-to-source (V) ofa short channel MOSFET with L_(g)=260 nm.

FIG. 13 is a plot of gate current (mAmps/mm) vs. gate voltage (V)comparing the gate leakage characteristics of a 260 nm MOSFET with a 200nm prior art HEMT.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a heterostructure including aIII-V semiconductor barrier layer and a III-V compound semiconductorchannel layer, FETs including the heterostructure as a buried channelstructure and methods of fabricating such structures, will now bedescribed in greater detail by referring to the following descriptionand drawings that accompany the present application. It is noted thatthe drawings of the present application are provided for illustrativepurposes only and, as such, the drawings are not drawn to scale. It isalso noted that in the drawings like reference numerals are used indescribing like materials.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill in the art that the invention may be practicedwithout these specific details. In other instances, well-knownstructures or processing steps have not been described in detail inorder to avoid obscuring the invention.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also hepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “beneath” or “under” another element, it can bedirectly beneath or under the other element, or intervening elements maybe present. In contrast, when an element is referred to as being“directly beneath” or “directly under” another element, there are nointervening elements present.

As stated above, the present invention provides a III-V compoundsemiconductor-containing heterostructure that includes a III-V compoundsemiconductor buffer layer having a first band gap, a III-V compoundsemiconductor channel layer having a second band gap located on an uppersurface of the buffer layer, and a III-V compound semiconductor barrierlayer having a third band gap located on an upper surface of the III-Vcompound semiconductor channel layer, wherein said first and third bandgaps are larger than the second band gap. An optional, yet preferred,III-V compound semiconductor cap layer can be present atop the barrierlayer. When present, the optional cap layer is typically doped,preferably with an n-type dopant for an N-MOSFET.

In the present invention, the term “III-V compound semiconductor”denotes a semiconductor material that includes at least one element fromGroup III of the Periodic Table of Elements and at least one elementfrom Group V of the Periodic Table of Elements. Typically, each of theIII-V compound semiconductor layers is a binary, ternary or quaternaryIII-V containing compound. Examples of III-V compound semiconductorsthat can be used in the present invention include, but are not limitedto alloys of InGaAs, InAlAs, InAlAsSb, InAlAsP and InGaAsP.

Reference is first made to FIG. 1 which illustrates the inventive III-Vcompound semiconductor-containing heterostructure 12 in accordance witha first embodiment of the present invention formed atop a surface of asemiconductor substrate 10. The inventive heterostructure 12 shown inFIG. 1 includes a III-V compound semiconductor buffer layer 14 having afirst band gap, a III-V compound semiconductor channel layer 16 having asecond band gap located on an upper surface of the III-V compoundsemiconductor buffer layer, and a III-V compound semiconductor barrierlayer 18 having a third band gap located on an upper surface of theIII-V compound semiconductor barrier layer 16.

In the embodiment illustrated, the barrier layer 18 includes a deltadoped region 18A that is located in a lower region of barrier layer 18abutting next to, but not in direct contact with, the interface (INT)with the underlying channel layer 16. The dopant atom present in thedelta doped region 18A may be an n-type dopant (i.e., an element fromGroup IV or VI of the Periodic Table of Elements) or a p-type dopant(i.e., an element from Group II or IV of the Periodic Table ofElements). The concentration of dopant within the delta doped region 18Ais typically from about 10¹¹ to about 10¹⁵ atoms/cm², with aconcentration of dopant within the delta doped region 18A from about10¹¹ to about 10¹³ atoms/cm² being even more typical.

The semiconductor substrate 10 employed in the present inventionincludes any semiconductor material including, for example, Si, SiGe,SiGeC, SiC, Ge alloys, Ga, GaAs, InAs, InP, Ge and all other III-Vcompound semiconductors. The semiconductor substrate 10 may comprise alayered semiconductor material such as, for example, asemiconductor-on-insulator. The semiconductor substrate 10 may be doped,undoped or contain doped and undoped regions therein. The semiconductorsubstrate 10 may have a single crystal orientation or it may havesurface regions that have different crystal orientations. Thesemiconductor substrate 10 may be strained, unstrained or a combinationthereof.

In accordance with the present invention, the band gap of the barrierlayer (i.e., the third band gap) is larger (wider) than the band gap ofthe channel layer (i.e., the second band gap). As stated above, the term“band gap” refers to the energy difference between the top of thevalence band (i.e., E_(V)) and the bottom of the conduction band (i.e.,E_(C)). Typically, the barrier layer 18 is comprised of a III-V compoundsemiconductor having a band gap value that is from about 0.5 to about 10times larger than the band gap of the III-V compound semiconductormaterial used in the channel layer 16. More typically, the barrier layer18 is comprised of a III-V compound semiconductor having a band gapvalue that is from about 1 to about 5 times larger than the band gap ofthe III-V compound semiconductor material used in the channel layer 16.FIG. 4 shows a typical band diagram of a MOSFET including the inventiveheterostructure shown in FIG. 2. In the band diagram E_(C) and E_(V) areas defined above, E_(F) representes the Fermi level and D_(it)represesents the interface state density.

The the band gap of the buffer layer 14 (i.e., the first band gap) isalso larger than that of the channel layer 16; this also helps toconfine the electrons within the channel layer as well. Typically, thebuffer layer 14 is comprised of a III-V compound semiconductor having aband gap value that is from about 0.5 to about 10 times larger than theband gap of the III-V compound semiconductor material used in thechannel layer 16. More typically, the buffer layer 14 is comprised of aIII-V compound semiconductor having a band gap value that is from about1 to about 5 times larger than the band gap of the III-V compoundsemiconductor material used in the channel layer 16.

It is noted that the band gap of the buffer layer and the band gap ofthe barrier layer, which are larger than the band gap of the channellayer, do not necessarily have the same value.

Since wide band gap materials are used for the barrier layer (and thebuffer layer as well) and a narrow band gap material is used for thechannel layer, carriers are confined to the channel layer under certaingate bias range. Typically, the carriers are confined in the channellayer when typical gate bias conditions are applied.

In a preferred embodiment of the present invention, the barrier layer 18and the buffer layer 14 are comprised of an alloy of InAlAs, while thechannel layer 16 is comprised of an alloy of InGaAs. By “alloy ofInAlAs” it is meant a composition of InxAl_(1-x)As wherein x is fromabout 0 to about 1, and more preferably from about 0.4 to about 0.6. Inone highly preferred embodiment of the present x is 0.52. By “alloy ofInGaAs” it is meant a composition of In_(y)Ga_(1-y)As wherein y is fromabout 0 to about 1, and more preferably y is from about 0.3 to about0.8. In an even highly preferred embodiment of the present invention, yis 0.7.

In_(0.32)Al_(0.48)As is an ideal high band gap material for the barrierlayer 18 since it has low electron affinity, about 4.03 eV, and itresults in a high conduction band offset relative to the channel layer16. A high barrier for electrons between the barrier layer 18 and thechannel 16 is achieved by using In_(0.7)Ga_(0.3)As as the low band gapmaterial for the channel layer 16. In_(0.7)Ga_(0.3)As channel can haveelectron mobility of greater than 10,000 cm²/Vs at room temperature. Inaddition, In_(0.7)Ga_(0.3)As has a higher electron affinity, 4.65 eV,than that of In_(0.52)Al_(0.48)As which can further increase theconduction band offset. However, oxidation of InAlAs poses a challengewhich needs to be addressed via proper surface passivation prior to gatedielectric deposition.

It is noted that each of the III-V compound semiconductor layersemployed in the present invention is a single crystal material oftypical commercial quality. By “typical commercial quality” it is meantthat each of the III-V compound semiconductor layers have a defectdensity on the order of about 10⁵ atoms/cm² or less, with a defectdensity of less than about 5000 atoms/cm² being more typical. Thetypical commercial quality of the III-V compound semiconductor layers isa result of utilizing an epitaxial growth process such as, for example,molecular beam epitaxy (MBE) or metalorgano chemical vapor deposition(MOCVD). That is, each of the III-V compound semiconductor layers areformed by an epitaxial growth process that produces a high quality,single crystal III-V film. The deposition of each of the III-V compoundsemiconductor layers of the preset invention may be performed in thesame or different apparatus. Moreover, each of the III-V compoundsemiconductor layers can be formed without breaking vacuum during thedeposition of each of the layers. Alternatively, vacuum may be brokenduring the formation of an individual III-V compound semiconductorlayer.

The III-V compound semiconductors are epitaxially grown utilizingIII/V-containing precursors that are well known to those skilled in theart. When the vacuum between the deposition of each of the III-V layersis not broken, the precursors can be switched to provide the next layer.In some embodiments, a graded III-V compound semiconductor layer can beformed.

When a delta doped region 18A is formed into the lower region of thebarrier layer 18A, an in-situ doping deposition process can be used inwhich the dopant atom is introduced during the initial formation of thebarrier layer and following the formation of a desired thickness of thedelta doped region (typically on the order of about 0.1 to about 2.0nm), the dopant is removed from the precursor stream and the barrierlayer 18 formation continues. Alternatively, the delta doped region 18Acan be formed utilizing ion implantation after the barrier layer 18 hasbeen formed. The conditions of such an implant are selected to provide adelta doped region next to, but not in contact with, the interface ofthe underlying channel layer 16.

Each of the individual III-V compound semiconductor layers shown in FIG.1 are thin (providing a total thickness of less than 600 nm). Typically,the buffer layer 14 has a thickness from about 25 to about 500 nm, witha thickness from about 100 to about 300 nm being even more typical. Thechannel layer 16 of the inventive structure has a thickness from about 1to about 15 nm, with a thickness from about 5 to about 10 nm being evenmore typical. The thickness of the barrier layer 18 of the inventivestructure is from about 0.1 to about 10 mn, with a thickness from about0.5 to about 10 nm being even more typical.

The applicants have formed a functional buried channelIn_(0.7)Ga_(0.3)As MOSFETs with a HfO₂ gate dielectric using a structuresimilar to that in FIG. 1, and have shown that these devices operatewith much reduced gate leakage compared to Schottky-gated devices.Extracted drift mobility of 6600 cm²V-s, at an apparent carrier densityof 3.2×10¹² cm⁻² was obtained.

Reference is now made to FIG. 2 which illustrates a preferredheterostructure 12′ that is formed atop a semiconductor substrate 10.The preferred heterostructure 12′ comprises a buffer layer 14, a channellayer 16, a non-doped barrier layer 18 and a III-V compoundsemiconductor cap layer 20.

The III-V semiconductor cap layer 20 is typically, but not alwaysnecessarily, a doped layer. The dopant within the III-V compoundsemiconductor cap layer 20 can be an n-type dopant or a p-type dopant,with an n-type dopant being more typical for an MOSFET. Unlike the deltadoped region 18A described above, the doping within the cap layer 20 isevenly distributed throughout the entire vertical thickness of thelayer. The concentration of dopant with the cap layer 20 is typicallyfrom about 10¹⁷ to about 10²¹ atoms/cm³, with a concentration of dopantwithin the cap layer from about 10¹⁸ to about 10²⁰ atoms/cm³ being moretypical.

The cap layer 20 may comprise the same or different III-V compoundsemiconductor as the channel layer 16. In a preferred embodiment of thepresent invention, the cap layer 20 comprises the same III-V compoundsemiconductor elements, but different alloy composition, as the channellayer 16 except for the presence of dopants within the cap layer 20.

The cap layer 20 is also a single crystal material of typical commercialquality since an epitaxial growth process such as MBE or MOCVD is usedin forming the same. The doping of the cap layer 20 typically occursduring the deposition of the cap layer Alternatively, the dopants can beintroduced into the cap layer 20 post deposition by ion implantation oroutdiffusion from a doped layer that is formed atop the cap layer 20.

The thickness of the cap layer 20 is from about 5 to about 50 nm, with athickness from about 15 to about 30 nm being even more typical.

In a preferred embodiment of the heterostructure 12′ shown in FIG. 2,the barrier layer 18 and the buffer layer 14 are comprised of an alloyof InAlAs, while the channel layer 16 and the cap layer 20 are comprisedof an alloy of InGaAs. The cap layer 20 is heavily doped with an n-typedopant. By “alloy of InAlAs” it is meant a composition ofIn_(x)Al_(1-x)As wherein x is from about 0 to about 1, and morepreferably from about 0.4 to about 0.6. In one highly preferredembodiment of the present x is 0.52. By “alloy of InGaAs” it is meant acomposition of In_(y)Ga_(1-y)As wherein y is from about 0 to about 1,and more preferably y is from about 0.3 to about 0.8. In a highlypreferred embodiment of the present invention, y is 0.7.

Reference is now made to FIG. 3 which illustrates a FET (i.e., MOSFET)structure of the present invention including the heterostucture 12′shown in FIG. 2 (with the cap layer patterned into patterned cap layer20′ having at least one opening 21) atop semiconductor substrate 10. Itis emphasized that although the FET shown in FIG. 3 includes theheterostructure 12′ of FIG. 2, the present invention also contemplates aFET in which the heterostructure 12 of FIG. 1 is used. When theheterostructure 12 shown in FIG. I is employed, the dielectric material(to be described herein below) is directly present on an upper surfaceof the barrier layer 18.

The FET 50 shown in FIG. 3 includes a semiconductor substrate 10 asdescribed above, a heterostructure 12′ as described above including apatterned cap layer 20 having an opening 21 that exposes a surface ofthe barrier layer 18, located on an upper surface of the semiconductorsubstrate 10, a dielectric material 30 located on the upper surface ofthe patterned cap layer 20 as well as within the opening 21 covering thesidewalls of the patterned cap layer 20′ and the exposed surface of thebarrier layer 18, a gate conductor 32 located on a portion of saiddielectric material 30 and above said opening 21, and source contact 34and a drain contact 36 abutting the outer edges of the dielectricmaterial 30 and extending into at least the channel layer 16; in thedrawing the source/drain contacts (34, 36) extend into the buffer layer14.

In FIG. 3, L_(g) denotes the gate length which is defined by thedistance of the remaining cap layer 20′ extending from the opening 21 toeither the source or drain contact (34, 36). In one embodiment, thechannel length is less than or equal to 260 nm. In some embodiments, thestructure has a positive threshold voltage.

The dielectric material 30 employed in the present invention has adielectric constant of greater than 4.0; such a dielectric material isreferred to hereafter as a high k dielectric. Typically, the high kdielectric 30 has a dielectric constant of about 7.0 or greater, with adielectric constant of about 10.0 or greater being even more typical.The dielectric constants mentioned herein are relative to a vacuum,unless otherwise stated. Specifically, the high k dielectric 30 employedin the present invention includes, but is not limited to an oxide,nitride, oxynitride and/or silicates including metal silicates,aluminates, titanates and nitrides. In one embodiment, it is preferredthat the high k dielectric 30 is comprised of HfO₂ ZrO₂, A1 ₂ 0 ₃, TiO₂,La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃, a pervoskite oxide, HfSiO_(z), HfAlO_(z) orHfAlO_(a)N_(b). Preferably, the high k dielectric 30 is a Hf-baseddielectric material.

The high k dielectric 30 is formed utilizing a conventional depositionprocess including, but not limited to molecular beam epitaxy (MBE),chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), atomic layer deposition (ALD), evaporation, physicalvapor deposition (PVD), chemical solution deposition and other likedeposition processes.

The thickness of the high k dielectric 30 may vary depending on thedeposition technique employed in fabricating the same as well as thecomposition and number of dielectrics of the high k dielectric.Typically, the high k dielectric 30 has a thickness from about 0.5 toabout 20 nm, with a thickness from about 1 to about 10 nm being highlypreferred.

The gate conductor 32 of the present invention includes any conductivematerial such as, for example, polysilicon, polysilicon germanium,conductive metals, conductive metal alloys, conductive silicides,conductive nitrides and combinations or multilayers thereof. Whenmetallic-containing gate conductors are employed, the metallic gateconductor can be doped so as to shift the workfunction of the gateconductor. Illustrative examples of dopant ions include As, P, B, Sb,Bi, Al, Ga, Ti or mixtures thereof. The same dopants are also used withpolysilicon or polySiGe mentioned above. Preferably, the gate conductor32 is a conductive metal, with Al, Pt, Au, W and Ti being highlypreferred. The selection of metal gates is advantageous since conductivemetals have different workfunctions that permit one to adjust thethreshold voltage of the device.

The gate conductor 32 is formed by a conventional deposition processsuch as, for example, CVD, PECVD, PVD, plating, thermal or ebeamevporation and sputtering. The gate conductor may be patterned bylithography and etching. Alternatively, the gate conductor 32 is formedby a conventional lift-off process.

The source and drain contacts (34, 36), which are on either side of thegate conductor 32, are typically comprised of a conductive materialincluding one of the conductive materials mentioned above for the gateconductor 32. The contacts are formed by lithography, etching a trenchinto the gate dielectric 30 and filling the trench with a conductivematerial.

In some embodiments of the present invention, the barrier layer 18 mayinclude a thin passivation layer (not shown). When present, the thinpassivation layer may comprise a thin layer of a chemical oxide.Alternatively, the passivation layer may include a thin layer ofamorphous Si/SiO₂ or Ge/Si/SiO₂. The thin passivation layer has athickness from about 0.5 to about 30 nm.

The optional passivation layer is formed by cleaning the surface of thebarrier layer 18 to remove any residual layers (e.g., native oxides),foreign particles, and any residual metallic surface contamination andto temporarily clean the barrier surface. Any residual oxide is removedin a solution of hydrofluoric acid, for example. Other wet etchingsolutions can also be used to form the optional passivation layer.Alternatively, treatment with a hydrogen plasma alone, or in conjunctionwith a chemical wet etchant may also be used to form the optionalpassivation layer.

In some embodiment, the dielectric material 30 not protected by the gateconductor 32 can be removed and a selective epitaxial semiconductorlayer can be formed adjacent the gate conductor to provides raisedsource/drain regions that lower the source/drain series resistance.Examples of selective epitaxial semiconductor layers that can be usedinclude, but are not limited to InGaAs having an In content that variesfrom 40 to 80% or Ge.

In the following example, an undopedIn_(0.7)Ga_(0.3)As/In_(0.52)Al_(0.48)As quantum well layer structure wasused as shown in FIG. 2. The layer structure was grown on an InPsubstrate, and consisted of a 300 nm In_(0.52)Al_(0.48)As buffer layer,a 10 nm strained In_(0.7)Ga_(0.3)As channel, a 10 nmIn_(0.52)Al_(0.48)As top barrier layer and a 25 nmn+−In_(0.53)Ga_(0.47)As cap layer. Aside from the topIn_(0.53)Ga_(0.47)As layer which was etched away in the gate region; alllayers were not-intentionally doped.

Device Fabrication

Long and short channel MOSFETs with metal gates and high k dielectricswere fabricated using the above layer structure. Long-channel ring FETdevices were made by patterning the heterostructure using opticallithography followed by selectively etching the InGaAs cap layer to forma gate recess area. After gate dielectric deposition, Ohmic contacts(i.e., source/drain contacts) were then formed. The gate regions werethen defined by optical lithography and metal lift off. Theshort-channel device fabrication included an additional mesa isolationstep before the gate lithography. In addition, the gate recess waspatterned by electron-beam lithography, where gate lengths as short as260 nm were fabricated. The long-channel devices utilized MBE-depositedHfO₂ and had Al gates, while the short-channel devices had ALD-Al₂O₃ asa gate dielectric and Al or Pt as the gate conductors.

Long-channel MOSFETs

The DC output characteristics of a typical buried In_(0.7)Ga_(0.3)Aschannel MOSFET with Lg=5 μm are shown in FIG. 5. The devices showed goodsaturation and pinch off characteristics. A series resistance of 128 Ωwas observed despite, the long channel length, an issue that may, inpart, be due to non-optimized contact formation. The sub-thresholdcharacteristics and corresponding transconductance are shown in FIGS.6A-6B. The devices operate in enhancement mode and had a thresholdvoltage of 0.25 V, as determined by linear extrapolation from the peaktransconductance at Vds=50 mV. The drain current on-off ratio wasapproximately 10⁴, and the devices had a sub-threshold slope of 150mV/decade. The extrinsic transconductance, g_(mext), had a peak value of23 mS/mm at Vds=1.2 V. The gate leakage characteristics are shown inFIG. 7, and were compared with prior art HEMTs. The gate leakage currentdensity of the MOSFET was more than 200× lower than the Schottky-gateddevices. The capacitance-voltage results for the MOSFETs are shown inFIG. 8. The effective-oxide thickness (EOT) extracted from the data was4.4+0.3 nm, The interface state density for these device was in the high10¹² cm⁻²/eV range, and this value could account for the non-idealsub-threshold slope. After correcting for the series resistance, theeffective drift mobility and the sheet density were calculated from theCg vs. Vgs (100 kHz) and linear Id-Vgs characteristics (Vds=50 mV). Theresulting mobility vs. sheet density plot is shown in FIG. 9. A peakmobility of 1100 cm²/Vs was determined at a carrier density of 2.6×10¹²cm⁻². Further improvements should be possible through optimization ofthe interface properties.

Short-Channel MOSFETs

As shown in FIG. 10, the short-channel MOSFETs (Lg=260 nm) had goodsaturation characteristics, but had high series resistance due to longaccess regions and non-ideal contacts. Depending upon the gate metalutilized, the devices were made to operate in both enhancement mode(Vt=+0.5 V), and depletion mode (Vt=−0.2 V), as shown in FIGS. 11 and12. The enhancement-mode devices had on-off ratio of approximately 10³at Vds=50 mV, and sub threshold slope of approximately 200 mV/dec (See,FIG. 11). For these devices, g_(mext), had a peak value of 43 mS/mm atVds=1.2 V. The gate leakage as in FIG. 13 shows considerable improvementover previous HEMT devices.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A semiconductor heterostructure comprising: a II-V compoundsemiconductor buffer layer having a first band gap; a III-V compoundsemiconductor channel layer having a second band gap located on an uppersurface of said buffer layer; and a III-V compound semiconductor barrierlayer having a third band gap located on an upper surface of the III-Vcompound semiconductor channel layer, wherein said first and third bandgaps are larger than the second band gap.
 2. The semiconductorheterostructure of claim 1 wherein said barrier layer includes a dopedregion which is located in a lower region of said barrier layer thatabuts an interface with the III-V compound semiconductor channel layer.3. The semiconductor heterostructure of claim 2 wherein said dopedregion has a dopant concentration from about 10¹¹ to about 10¹⁵atoms/cm².
 4. The semiconductor heterostructure of claim 2 wherein saiddoped region includes an element from Group IV, II or VI or the PeriodicTable of Elements as a dopant.
 5. The semiconductor heterostructue ofclaim 1 further comprising a III-V compound semiconductor cap layerlocated atop the III-V compound semiconductor barrier layer.
 6. Thesemiconductor heterostructure of claim 5 wherein said cap layer includesan n-type dopant.
 7. The semiconductor heterostructure of claim 5wherein said cap layer comprises the same or different II-V compoundsemiconductor as the channel layer.
 8. The semiconductor heterostructureof claim 1 wherein said barrier layer and said buffer layer arecomprised of an alloy of InAlAs, while said channel layer is comprisedof an alloy of InGaAs.
 9. The semiconductor heterostructure of claim 8wherein said alloy of InAlAs has the formula In_(x)Al_(1-x)As wherein xis from about 0.4 to about 0.6, and said alloy of InGaAs has the formulaIn_(y)Ga_(1-y)As wherein y is from about 0.3 to about 0.8.
 10. Thesemiconductor heterostructure of claim 8 wherein said alloy of InAlAs isIn_(0.52)Al_(0.48)As and said alloy of InGaAs is In_(0.7)Ga_(0.3)As. 11.The semiconductor heterostructure of claim 1 wherein each of said III-Vcompound semiconductor layers is a single crystal material having adefect density on the order of about 10⁵ atoms/cm² or less.
 12. Thesemiconductor heterostructure of claim 1 wherein said buffer layer has athickness from about 25 to about 500 nm, said channel layer has athickness from about 1 to about 15 nm and said barrier layer has athickness from about 0.1 to about 10 nm.
 13. A semiconductor structurecomprising: a semiconductor substrate having an upper surface; a buriedchannel structure located on said upper surface of said semiconductorsubstrate, wherein said buried channel structure comprises a III-Vcompound semiconductor buffer layer having a first band gap located atopsaid upper surface of said semiconductor substrate, a III-V compoundsemiconductor channel layer having a second band gap located on saidbuffer layer, and a III-V compound semiconductor barrier layer having athird band gap located on an upper surface of the III-V compoundsemiconductor channel layer, wherein said first and third band gaps arelarger than the second band gap; a dielectric material having adielectric constant of greater than 4.0 located on said buried channelstructure and in contact with at least a portion of said barrier layer;a gate conductor located on a portion of said dielectric material; and asource contact and a drain contact which are in contact with at leastsaid channel layer.
 14. The semiconductor structure of claim 13 whereinsaid barrier layer includes a doped region which is located in a lowerregion of said barrier layer that abuts an interface with the III-Vcompound semiconductor channel layer.
 15. The semiconductor structure ofclaim 14 wherein said doped region has a dopant concentration from about10¹¹ to about 10¹⁵ atoms/cm².
 16. The semiconductor structure of claim14 wherein said doped region includes an element from Group IV, II or VIor the Periodic Table of Elements as a dopant.
 17. The semiconductorstructure of claim 13 further comprising a patterned III-V compoundsemiconductor cap layer located atop the III-V compound semiconductorbarrier layer, said patterned cap layer having an opening that exposessaid barrier layer.
 18. The semiconductor structure of claim 17 whereinsaid patterned cap layer includes an n-type dopant.
 19. Thesemiconductor structure of claim 17 wherein said patterned cap layer isdoped with a dopant, said dopant is present within said cap layer in aconcentration from about 10¹⁷ to about 10²¹ atoms/cm³.
 20. Thesemiconductor structure of claim 17 wherein said patterned cap layercomprises the same or different III-V compound semiconductor as thechannel layer.
 21. The semiconductor structure of claim 16 wherein saidbarrier layer and said buffer layer are comprised of an alloy of InAlAs,while said channel layer is comprised of an alloy of InGaAs.
 22. Thesemiconductor structure of claim 21 wherein said alloy of InAlAs has theformula In_(x)Al_(1-x)wherein x is from about 0.4 to about 0.6, and saidalloy of InGaAs has the formula In_(y)Ga_(1-y) wherein y is from about0.3 to about 0.8.
 23. The semiconductor structure of claim 21 whereinsaid alloy of InAlAs is In_(0.52)Al_(0.48)As and said alloy of InGaAs isIn_(0.7)Ga_(0.3)As.
 24. The semiconductor structure of claim 13 whereineach of said III-V compound semiconductor layers is a single crystalmaterial having a defect density on the order of about 10⁵ atoms/cm² orless.
 25. The semiconductor structure of claim 13 wherein said bufferlayer has a thickness from about 25 to about 500 nm, said channel layerhas a thickness from about 1 to about 15 nm and said barrier layer has athickness from about 0.1 to about 10 nm.
 26. The semiconductor structureof claim 13 wherein said dielectric material comprises HfO₂, ZrO₂,Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃, a pervoskite oxide, HfSiO_(z),HfAlO₂ or HfAlO_(a)N_(b).
 27. The semiconductor structure of claim 13wherein said gate conductor comprises polysilicon, polysilicongermanium, a conductive metal, a conductive metal alloy, a conductivesilicide, a conductive nitride or combinations and multilayers thereof28. The semiconductor structure of claim 13 wherein said source contactand said drain contact comprise polysilicon, polysilicon germanium, aconductive metal, a conductive metal alloy, a conductive silicide, aconductive nitride and combinations or multilayers thereof.
 29. Thesemiconductor structure of claim 13 wherein said structure has apositive threshold voltage and having a gate length of less than orequal to 260 nm.
 30. A method of fabricating a III-V compoundsemiconductor-containing heterostructure comprising: first epitaxiallygrowing a III-V compound semiconductor buffer layer having a first bandgap on an upper surface of a substrate; second epitaxially growing aIII-V compound semiconductor channel layer having a second band gap onan upper surface of said buffer layer; and third epitaxially growing aIII-V compound semiconductor barrier layer having a third band gap on anupper surface of the III-V compound semiconductor channel layer, whereinsaid first and third band gaps are larger than the second band gap. 31.The method of claim 30 further comprising a fourth epitaxially growingstep that forms a III-V compound semiconductor cap layer on the surfaceof the barrier layer.
 32. A method of fabricating a FET comprising:forming a buried channel structure located on an upper surface of asemiconductor substrate, wherein said forming comprises firstepitaxially growing a III-V compound semiconductor buffer layer having afirst band gap on a said upper surface of said substrate, secondepitaxially growing a III-V compound semiconductor channel layer havinga second band gap on an upper surface of said buffer layer, and thirdepitaxially growing a III-V compound semiconductor barrier layer havinga third band gap on an upper surface of the channel layer, wherein saidfirst and third band gaps are larger than the second band gap; forming adielectric material having a dielectric constant of greater than 4.0located on said buried channel structure and in contact with at least aportion of said barrier layer; forming a gate conductor located on aportion of said dielectric material; and forming a source contact and adrain contact which are in contact with at least said channel layer. 33.The method of claim 32 further comprising forming a patterned III-Vcompound semiconductor cap layer having at least one opening thatexposes a surface of said barrier layer, said forming comprises a fourthepitaxial growing step, lithography and etching.